1. Field of the Invention
The present invention generally relates to the field of fabrication of integrated circuits, and, more particularly, to the formation of metal layers over a patterned dielectric material comprising trenches and vias by a wet chemical deposition process.
2. Description of the Related Art
In an integrated circuit, a huge number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits for advanced applications, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as the mechanical, thermal and electrical reliability of the plurality of stacked metallization layers that are required, for example, for sophisticated based microprocessors, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections. For example, copper is a metal generally considered to be a viable candidate for replacing aluminum, due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures, due to copper's characteristic to form non-volatile reaction products. In manufacturing metallization layers including copper, the so-called damascene inlaid technique is therefore preferably used, wherein a dielectric layer is first applied and then patterned to define trenches and vias therein, which are subsequently filled with the metal, such as copper.
A further major drawback of copper is its propensity to readily diffuse in silicon dioxide and other dielectric materials. It is therefore usually necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may then readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. Moreover, in view of copper integrity, the barrier material may be selected to suppress diffusion of unwanted materials, such as oxygen, fluorine and the like, towards the copper, thereby reducing the risk for corrosion and oxidation. Since the dimensions of the trenches and vias have currently reached a width or a diameter of approximately 0.1 μm and even less, with an aspect ratio of the vias of about 5 or more, the reliable deposition of a barrier layer on all surfaces of the vias and trenches and the subsequent filling thereof with copper substantially without voids is a most challenging issue in the fabrication of modern integrated circuits.
Currently, the formation of a copper-based metallization layer is accomplished by patterning an appropriate dielectric layer and depositing the barrier layer, for example comprised of tantalum (Ta) and/or tantalum nitride (TaN), by advanced physical vapor deposition (PVD) techniques, such as sputter deposition. For the deposition of a barrier layer of approximately 10 to 50 nm in vias having an aspect ratio of 5 or even more, enhanced sputter tools are usually employed. Such tools offer the possibility of ionizing a desired fraction of the target atoms after sputtering them off the target, thereby enabling, to a certain degree, the control of the bottom coverage and the sidewall coverage in the vias. Thereafter, the copper is filled in the vias and trenches, wherein electroplating has proven to be a viable process technique, since it is capable of filling the vias and trenches with a high deposition rate, compared to CVD and PVD rates, in a so-called bottom-up regime, in which the openings are filled starting at the bottom in a substantially void-free manner. Generally, in electroplating a metal, an external electric field is applied between the surface to be plated and the plating solution. Since substrates for semiconductor production may be contacted at restricted areas, usually at the perimeter of the substrate, a conductive layer covering the substrate and the surfaces that are to receive a metal has to be provided. Although the barrier layer previously deposited over the patterned dielectric may act as a current distribution layer, it turns out, however, that, in view of crystallinity, uniformity and adhesion characteristics, a so-called seed layer is usually required in the subsequent electroplating process to obtain copper trenches and vias having the required electrical and mechanical properties. The seed layer, usually comprised of copper, is typically applied by sputter deposition using substantially the same process tools as are employed for the deposition of the barrier layer.
For dimensions of 0.1 μm and less of vias in future device generations, the sputter deposition of extremely thin metal layers having a high degree of conformity as required for the barrier layer and the seed layer may become a limiting factor, since the step coverage characteristics of the above-described advanced sputter tools may not be further enhanced without significant modifications of these tools, which seems to not be a straightforward development. Especially, the deposition of the seed layer may not be performed in a straightforward manner by PVD, as here the uniformity of the seed layer determines, to a certain degree, the uniformity of the following electroplating process, contrary to the barrier layer “only” requiring a sufficient and complete coverage of the inner surfaces of the openings. Moreover, PVD techniques producing extremely thin layers appropriate for barrier layers may result in an increased electric resistance when applied to the formation of seed layers, thereby reducing an initial deposition rate of the subsequent electroplating process.
As a consequence, alternative deposition techniques for highly sophisticated applications have been proposed for barrier deposition and seed deposition for copper-based lines. For example, CVD techniques have been developed for forming highly conformal barrier and seed layers, thereby taking advantage of CVD's inherent superior behavior with respect to step coverage compared to sputter deposition. Similarly, self-limiting CVD-based deposition techniques known as atomic layer deposition (ALD) have been developed for several materials in order to provide extremely thin yet reliable barrier or seed layers within high aspect ratio openings. However, it seems that these techniques, although per se offering advantages in terms of layer consistency and coverage, result in less desirable properties of the copper metal after the subsequent electroplating process. In particular, seed layers may be inferior to commonly used PVD seed layers due to a significant incorporation of contaminants, thereby resulting in higher electric resistance and weak texture that may, in turn, entail nearly randomly textured metal films.
In view of the above-explained situation, a need exists for an enhanced technique enabling the efficient deposition of metal within high aspect ratio openings by a wet chemical deposition process, thereby avoiding or at least reducing one or more of the above-identified problems.